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[VHDL-FPGA-Verilog] uart

Description: 关于串口发送的verilog代码，实验中经常用到，已经用FIFO-it is about the uart transmit verilog code,very useful in experiment.
Platform: | Size: 3072 | Author: 李sir | Hits:

[VHDL-FPGA-Verilog] uart_1203_4

Description: MUC+fpga 串口扩展，已调试通过，4路串口共用中断，收发fifo，波特率可调，其他的可以自己添加，网上类似资料极少，极具参考价值！只提供verilog源码！-MUC+ fpga McU.that, already debugging, through, 4 road serial common interrupt, receiving and dispatching fifo, baud rate can be adjusted, the other can add your own, online similar material is few, most reference value! Provide only verilog source!
Platform: | Size: 2239488 | Author: 李康 | Hits:

[VHDL-FPGA-Verilog] System_Demons

Description: 0.最简单的SystemC程序：hello, world. 1.用SystemC实现D触发器的例子，同时也演示了如何生成VCD波形文件。 2.用SystemC实现同步FIFO的例子。这个FIFO是从同文件夹的fifo.v（verilog代码）翻译过来的。 3.如何在SystemC中实现延时（类似verilog中的#time）的例子。 4.SystemC文档《User Guide》中的例子。注意和文挡中稍有不同的是修改了packet.h文件，重载了=和<<操作符。这其实也演示了在sc_signal中如何使用用户自定义的struct。 5.构造函数带参数的例子。 6.轮转仲裁的例子。 7.使用类摸板的例子。 8.如何在模块中包含子模块。 9.SystemC的Transaction级验证示例。 10.如何trace一个数组 11.SystemC中使用测试向量文件输入的例子。 12.SystemC采用UDP/TCP通信的例子。 13.Cadence的ncsc的例子。 -0 most simple SystemC program: hello, world. A D flip-flop using SystemC example also demonstrates how to generate VCD waveform files. Synchronous FIFO example using SystemC. FIFO is from the same folder fifo.v (Verilog code) translated. Delay (similar to verilog# time). In SystemC examples. 4.SystemC document the "User Guide" in the example. Note the slightly different cultural block is modified the packet.h file, reload = << operator. In fact, this also demonstrates how to use user-defined struct in sc_signal. Constructor with parameters example. (6) examples of web arbitration. 7. The class Moban examples. 8 module contains a sub-module. 9.SystemC of Transaction-Level Verification example. 10 How to trace an array 11.SystemC use the example of the test vector file input. 12.SystemC using the example of the UDP/TCP communication. Examples of 13.Cadence the ncsc.
Platform: | Size: 532480 | Author: sdd | Hits:

[VHDL-FPGA-Verilog] FIFO2

Description: 用verilog HDL语言编写的fifo存储器源文件 -Using Verilog language HDL FIFO memory source file
Platform: | Size: 1481728 | Author: 王浩宇 | Hits:

[VHDL-FPGA-Verilog] fifo_uart

Description: 使用fifo完成的串口通信。verilog语言。-fifo-uart verilog
Platform: | Size: 3072 | Author: 曹曹 | Hits:

[VHDL-FPGA-Verilog] Syn_FIFO

Description: 基于Actel公司的开发平台，verilog实现同步fifo设计-Double port ROM verilog realization, based on the development of the Actel development platform based on Actel company development platform, verilog simultaneous fifo design
Platform: | Size: 2820096 | Author: 林鸿海 | Hits:

[VHDL-FPGA-Verilog] uartfifo

Description: verilog实现的fifo到串口数据通信-verilog achieve fifo to the serial data communication
Platform: | Size: 633856 | Author: 唐华 | Hits:

[VHDL-FPGA-Verilog] versatile_fifo_latest.tar

Description: Verilog HDL语言编写的通用FIFO，让你更加了解FIFO的原理-versatile fifo based on verilog hdl.
Platform: | Size: 1293312 | Author: troy | Hits:

[VHDL-FPGA-Verilog] async_fifo

Description: 用verilog语言编写并经过综合验证的异步FIFO的源代码-the verilog code of asynchronizing fifo
Platform: | Size: 476160 | Author: 马腾宇 | Hits:

[VHDL-FPGA-Verilog] uartfifo

Description: 利用verilog开发的串口FIFO程序，比较基本，包含完整的工程-The verilog developed serial FIFO procedures, more basic, including the complete project
Platform: | Size: 2276352 | Author: 给他 | Hits:

[VHDL-FPGA-Verilog] FIFOUART

Description: fpga实现的基于FIFO的异步串行通信代码，描述语言为Verilog-fpga-based FIFO asynchronous serial communication code description language Verilog
Platform: | Size: 2048 | Author: jiangliang | Hits:

[VHDL-FPGA-Verilog] fifo_ctrl

Description: 好用的fifo控制verilog源代码，供大家学习参考，可以被综合。-Useful fifo control verilog source code for the study reference, can be integrated.
Platform: | Size: 6144 | Author: mmmm1111111111 | Hits:

[VHDL-FPGA-Verilog] 024-DAC902

Description: verilog控制dac902的程序，先从fifo读取数据-the verilog control the dac902 procedures start fifo read data
Platform: | Size: 105472 | Author: Lawrence | Hits:

[VHDL-FPGA-Verilog] 022-FIFO_PRO

Description: verilog写的控制quartus自带fifo ip核的程序-verilog to write the control quartus own fifo ip nuclear program
Platform: | Size: 993280 | Author: Lawrence | Hits:

[OS program] aFIFO

Description: 实现了一个异步fifo功能的verilog模块-An asynchronous fifo function verilog module
Platform: | Size: 2048 | Author: 董萱 | Hits:

[Windows Develop] VFIFOzipe

Description: 用verilog实现异步FIFO，代码中有两个模块，使用时时注意顶层模块和底层模块，用quartus2即可打开直接使用。 -Asynchronous FIFO, with verilog code has two modules, using the constant attention of top-level module and bottom module with quartus2 to open.
Platform: | Size: 2048 | Author: zcl1233 | Hits:

[VHDL-FPGA-Verilog] sram_fifo_uart

Description: 用verilog HDL编写的SRAM+FIFO+UART模块，欢迎各位指点 -Welcome to the guidance written in verilog HDL SRAM+FIFO+UART module
Platform: | Size: 2302976 | Author: 钱世俊 | Hits:

[VHDL-FPGA-Verilog] fifo_ctrl

Description: fifoctr 寄存器控制 verilog代码-FIFO ctr
Platform: | Size: 1024 | Author: 岳雪 | Hits:

[Windows Develop] aasyn_fiffos

Description: verilog编写的异步fifo源代码，asyn_fiifo.v为顶层，调用其他四个文件， -verilog prepared the the asynchronous fifo source code, asyn_fiifo.v for the top floor, calling the other four documents,
Platform: | Size: 2048 | Author: mmzz3211 | Hits:

[VHDL-FPGA-Verilog] LL

Description: verilog语言描述的异步FIFO设计。-verilog language to describe the asynchronous FIFO design.
Platform: | Size: 6144 | Author: whh | Hits:
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